? semiconductor components industries, llc, 2002 april, 2002 rev. 5 1 publication order number: mc10e431/d mc10e431, mc100e431 5vecl 3bit differential flipflop the mc10e/100e431 is a 3-bit flip-flop with differential clock, data input and data output. the asynchronous set and reset controls are edge-triggered rather than level controlled. this allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). the e431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window. the differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. the clamping action will assert the d and the clk sides of the inputs. because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. note that the input clamps only operate when both inputs fall to 2.5 v below v cc . the 100 series contains temperature compensation. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? edge-triggered asynchronous set and reset ? differential d, clk and q; v bb reference available ? 1100mhz min. toggle frequency ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 1 kv hbm, > 75 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 348 devices device package shipping ordering information mc10e431fn plcc28 37 units/rail mc10e431fnr2 plcc28 500 units/reel mc100e431fn plcc28 37 units/rail mc100e431fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e431fn awlyyww mc100e431fn awlyyww 128 128 http://onsemi.com
mc10e431, mc100e431 http://onsemi.com 2 clk0 clk0 d 0 d 0 r 0 d 2 d 2 clk2 clk2 v bb v cco clk1 clk1 r 1 v ee s 1 d 1 d 1 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 567 8910 r 2 s 2 q 2 q 2 v cc q 1 q 1 q 0 q 0 s 0 1 pinout: 28-lead plcc (top view) * all v cc and v cco pins are tied together on the die. logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin function d [ 0:2 ] , d [ 0:2 ] ecl differential data inputs clk [ 0:2 ] , clk [ 0:2 ] ecl differential clock s [ 0:2 ] ecl edge triggered set inputs r [ 0:2 ] ecl edge triggered reset input q [ 0:2 ] , q [ 0:2 ] ecl differential data outputs v bb reference voltage output v cc , v cco positive supply v ee negative supply function table dn clkn rn sn qn l z l l l h z l l h x x z l l x x l z h z = low to high transition x = don't care logic diagram s 0 d 0 d 0 clk0 clk0 r 0 s 1 d 1 d 1 clk1 clk1 r 1 s 2 d 2 d 2 clk2 clk2 r 2 v bb q 0 q 0 q 1 q 1 q 2 q 2 s q r q d s q r q d s q r q d
mc10e431, mc100e431 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 110 132 110 132 110 132 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (single ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage (single ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv v bb output voltage reference 3.62 3.63 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 3) 2.7 5.0 2.7 5.0 2.7 5.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 110 132 110 132 110 132 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage (single ended) 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage (single ended) 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv v bb output voltage reference 1.38 1.37 1.35 1.25 1.31 1.19 v v ihcmr input high voltage common mode range (differential) (note 3) 2.3 0.0 2.3 0.0 2.3 0.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e431, mc100e431 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 110 132 110 132 127 152 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (single ended) 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage (single ended) 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 3) 2.7 5.0 2.7 5.0 2.7 5.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 110 132 110 132 127 152 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage (single ended) 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage (single ended) 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3) 2.3 0.0 2.3 0.0 2.3 0.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e431, mc100e431 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd 1.1 tbd ghz t plh t phl propagation delay to output clk (diff) clk (se) r s 410 460 500 500 600 600 725 725 790 840 975 975 450 400 550 550 600 600 725 725 750 800 925 925 450 400 550 550 600 600 725 725 750 800 925 925 ps t s setup time d r (note 1.) s (note 1.) 250 1100 1100 0 700 700 200 1000 1000 0 700 700 200 1000 1000 0 700 700 ps t h hold time d 250 0 200 0 200 0 ps t pw minimum pulse width clk 400 400 400 ps t skew within-device skew (note 2.) 50 50 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp minimum input swing (note 3.) 150 1000 150 1000 mv t r /t f rise/fall times (2080%) 250 450 700 275 450 650 ps 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. 1. these setup times define the minimum time the clk or set/reset input must wait after the assertion of the reset/set input to assure the proper operation of the flip-flop. 2. within-device skew is defined as identical transitions on similar paths through a device. 3. minimum input swing for which ac parameters are guaranteed. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt
mc10e431, mc100e431 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e431, mc100e431 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.004 (0.100) seating plane -t- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d-d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc -n- y brk d d w -m- -l- 28 1 v g1 k1
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